In integrated semiconductor memories, for example DRAM (Dynamic Random Access Memory) semiconductor memories, memory operations are generally triggered upon rising and falling edges of clock signals. For this purpose, the integrated semiconductor memory is driven with an external clock signal by a memory controller. The external clock signal is fed to a clock generator circuit in the semiconductor memory. The clock generator circuit generates, from the clock signals fed to it externally, an internal clock signal having a higher frequency and phase stability than the external clock signal.
FIG. 4 shows an integrated semiconductor memory 100 having a clock generator circuit 10 for generating an internal clock signal Cint. The integrated semiconductor memory has a clock terminal T100a for application of an external clock signal Cext and a clock terminal T100b for application of a reference signal Vref. The external clock signal Cext and the reference signal Vref are fed to the clock generator circuit 10 via input terminals E10a and E10b connected to the clock terminals T100a and T100b. After evaluation of the two signals, the clock generator circuit 10 generates the internal clock signal Cint at an output terminal A10, said internal clock signal being fed to a control circuit 20. The control circuit 20 is connected to a control terminal S100 of the integrated semiconductor memory via an input terminal E20. For the purpose of storing data and for the purpose of reading out data, the control circuit 20 is driven with external control signals at the control terminal S100. In this case, the external control signals are read in and evaluated by the control circuit 20 synchronously with respect to rising and falling edges of the internal clock signal Cint. The integrated semiconductor memory furthermore has an address register 30, which, on the input side, is connected to an address terminal A100 for application of address signals AS. The address signals AS are buffer-stored in the address register 30 and fed to the control circuit 20.
For a read and write access, the control circuit 20 evaluates the address signals AS upon rising and falling clock edges of the internal clock signal Cint and drives memory cells SZ associated with the addresses in a memory cell array 40. Two memory cells SZ, designed as DRAM memory cells, are illustrated by way of example in the memory cell array 40. The DRAM memory cells SZ have a storage capacitor SC that can be conductively connected to a bit line BL via a selection transistor AT. In order to read out a data value from the memory cell or in order to write a data value to the memory cell, the selection transistor is turned on by means of a signal on a word line WL that is generated by the control circuit 20. In the event of a read access, the memory information is read out via the bit line BL at a data terminal DIO. In the event of a write access, a data value to be written in is applied to the data terminal DIO and written to the memory cell via the bit line BL.
FIG. 5 illustrates the functioning of the clock generator circuit 10. The diagrams in each case show the profile of a voltage amplitude U of external and internal clock signals against a time t.
The first diagram of FIG. 5 shows the profile of an external clock signal Cext1. In this case, the voltage amplitude fluctuates between a high first clock signal level PE1 and a low second clock signal level PE2 during a pulse duration TD.
The second diagram of FIG. 5 shows the profile of the internal clock signal Cint generated by the clock generator circuit 10 in the case of driving with the external clock signal Cext1 of the first diagram of FIG. 5. In this case, the voltage amplitude of the internal clock signal fluctuates between a first high level PI1 and a second low level PI2. If the voltage amplitude of the external clock signal Cext1 exceeds a sensitivity level Vref of the clock generator circuit 10, the clock generator circuit 10 generates the internal clock signal with the high level PI1. If, by contrast, the voltage amplitude of the external clock signal Cext1 falls below the sensitivity level Vref (crossing point), the clock generator circuit 10 generates the internal clock signal with the low level PI2.
A sensitivity time TE of the clock generator circuit 10 is furthermore depicted in the first diagram of FIG. 5. In this case, the sensitivity time TE is the time for which the voltage amplitude of the external clock signal must be present at least at the clock generator circuit 10 in order that the clock generator circuit 10 can generate the first or second level of the internal clock signal Cint. A change in the amplitude of the external clock signal above or below the value of the reference signal is thus interpreted by the clock generator circuit 10 as a change between the two levels of the internal clock signal PI1 and PI2 only when the external clock signal assumes an amplitude value above or below the reference signal Vref at least for the time period of the sensitivity time TE.
The third diagram of FIG. 5 shows an external clock signal Cext2 having a lower signal/noise ratio than the external clock signal Cext1. The fourth diagram of FIG. 5 shows the profile of the internal clock signal Cint if the clock generator circuit 10 is driven by the noisy signal level of the external clock signal Cext2 of diagram 3. The internal clock signal Cint exhibits a plurality of changes between the high and low level of the internal clock signal PI1 and PI2 in particular at the rising and falling edges F1 and F2 of the external clock signal Cext2. These high-frequency changes in the internal clock signal arise by virtue of the fact that the signal amplitude of the noisy external clock signal Cext2, in the region of the rising and falling edges, repeatedly lies above and below the level of the reference signal Vref. The input noise (jitter) of the external clock signal thereby leads to an uncontrolled switching behavior of the internal chip logic.
FIG. 6 shows an embodiment of the clock generator circuit 10 corresponding to the prior art. The clock generator circuit is designed as a differential amplifier connected between a terminal V10a for application of a supply voltage VDD and a terminal V10b for application of a reference voltage VSS. The differential amplifier has a first input transistor 13, which is connected by its control terminal to the input terminal E10a of the clock generator circuit, and a second input transistor 14, which is connected by its control terminal to the input terminal E10b of the clock generator circuit.
In contrast to the simplified embodiment of the clock generator circuit of FIG. 4, the differential amplifier in FIG. 6 is driven by a first external clock signal CLK and an external clock signal /CLK complementary thereto. Such driving is generally used in a computer application if the integrated semiconductor memory is driven by a memory controller, for example. The clock generator circuit generates a low to high or high to low level transition if the profile of the amplitude of the first external clock signal CLK intersects the profile of the amplitude of the second external clock signal /CLK (crossing point). A current source 17b generates a current I at a common terminal GS of the input transistors 13 and 14. Furthermore, the input transistors 13 and 14 are connected via an active load comprising the transistors 15 and 16, which are connected up as a current mirror, to the terminal V10a for application of the supply voltage VD. On the output side, the differential amplifier generates an output signal DS, which is fed to a latch 18. The latch comprises two feedback inverters 19a and 19b connected to the output terminal A10 of the clock generator circuit 10. The inverter 19a generates the high or low level of the internal clock signal Cint on the output side. It is generally designed as an amplifier having a high gain, whereas the inverter 19b is designed as an amplifier having a low gain. The feedback via the inverter 19b acts as a positive feedback. The positive feedback prevents the changeover of the differential amplifier in the event of momentary amplitude fluctuations of the input clock signal CLK.
The circuit described makes it possible to significantly reduce the generation of undesired clock signal transitions of the internal clock signal on account of a noisy external input clock signal. However, the disadvantage of this solution to the problem lies in the positive feedback, which leads to a reduced sensitivity of the differential amplifier with regard to level fluctuations of the external clock signal at its input terminals E10a and E10b. In the case of weak external clock signals having a low high level or a high low level, the high-low or low-high transitions of the external clock signal are no longer identified by the differential amplifier. Furthermore, the frequency of the internal clock signal which can be generated by means of the differential amplifier 10 is limited by the intensity of the feedback. The clock generator circuit is thereby slowed down.
It is also disadvantageous that the so-called duty cycle of the clock generator circuit, which characterizes the ratio of high/low times becomes highly process-dependent as a result of the positive feedback. Changes in the saturation current of the p-channel and/or n-channel transistors of the inverters 19a and 19b cause the feedback of the high and low levels to have different intensities in the case of the positive feedback. The duty cycle for weak or very high-frequency external clock signals is considerably impaired as a result.
The process dependence of the feedback also has a problematic effect in particular when the differential amplifier 10, as shown in FIG. 4, is driven at its second input transistor 14 by a constant reference signal Vref rather than by the complementary external clock signal /CLK. Integrated semiconductor memories are driven by a constant level of a reference signal at one of the clock terminals by test systems for test purposes, in particular.